1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method and system for polishing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Fabrication of an integrated circuit involves numerous processing steps. For example, isolation regions may be formed in the semiconductor substrate to separate subsequently formed active regions of the substrate. In addition, after implant regions (e.g., source/drain regions) have been placed within a semiconductor substrate and gate areas defined upon the substrate, an interlevel dielectric may be formed across the topography to isolate the gate areas and the implant regions from overlying conductors. Interconnect routing may then placed over the interlevel dielectric and connected to the implant regions and/or the gate areas by ohmic contacts formed through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
Forming substantially planar upper surfaces of a semiconductor topography during intermediate process steps may facilitate fabrication of layers and structures that meet design specifications. For example, a dielectric layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d). Such a dielectric layer may be used to form an interlevel dielectric or shallow trench isolation regions. Elevational disparities of the deposited dielectric layer may be reduced by polishing the deposited dielectric layer using a process such as chemical mechanical polishing (xe2x80x9cCMPxe2x80x9d). In an embodiment in which the dielectric layer is an interlevel dielectric, a contact opening may be formed within the polished dielectric layer and subsequently filled with a layer of conductive material. In this manner, the layer of conductive material may be formed within the contact opening and on an upper surface of the polished dielectric layer. As such, the layer of conductive material may also be polished such that an upper surface of the contact structure may be relatively level with an upper surface of the dielectric layer.
Additional layers and structures may be formed upon such layers and structures. The additional layers and structures may include, for example, additional dielectric layers, additional contact structures, local interconnect wires, and/or metallization layers. In this manner, the polished upper surface of the dielectric layer and/or structures may facilitate the formation of such additional layers and structures having uniform vertical and lateral dimensions. For example, the polishing of the semiconductor topography may facilitate the formation of local interconnect structures having a substantially uniform thickness by providing a relatively planar surface upon which a dielectric material may be deposited to insulate adjacent local interconnect structures.
Moreover, the polishing of the semiconductor topography may aid in forming local interconnect structures having uniform lateral dimensions by providing a level surface upon which a patterned masking layer may be formed. In this manner, a masking layer may be accurately patterned by a lithography technique such that the pattern may be accurately transferred to a dielectric layer to form local interconnect structures. In another embodiment, the polishing of the semiconductor topography may include forming shallow trench isolation regions with substantially planar surfaces such that the aforementioned additional layers and structures may be formed with uniform thickness and with lateral dimensions within specification. Accordingly, layers and structures of a semiconductor device may be formed having dimensions which are approximately equal to the design specifications of the semiconductor device.
Forming a substantially planar upper surface of such layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and raised regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. In addition, if a topography is non-planar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. In particular, correctly patterning layers upon a topological surface containing elevational xe2x80x9chillxe2x80x9d or xe2x80x9cvalleyxe2x80x9d areas may be difficult using optical lithography since the all parts of the topography must be within the depth of focus of the lithography system.
As mentioned above, CMP is a technique commonly employed to polish or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer against a backing plate of a wafer carrier in order to hold the wafer relative to an underlying polishing pad. The wafer may then be pressed face-down toward the polishing pad which lies on or is attached to a support structure. During the CMP process, the polishing pad and/or the wafer carrier may be set in motion as the wafer is forced against the pad. For example, the polishing pad and the wafer carrier may be placed on a rotatable table such that the wafer and the polishing pad may be rotated relative to each other. Alternatively, the wafer carrier may be rotated relative to a fixed pad or vice versa. In another embodiment, the polishing pad may be a belt, which traverses against a fixed or rotating wafer. In either embodiment, the rotatable table, fixed pad, or belt may serve as the support structure to which the polishing pad lies upon or is attached.
An abrasive, fluid-based chemical suspension, often referred to as a xe2x80x9cslurry,xe2x80x9d may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. In addition, the pad itself may physically remove some material from the surface of the semiconductor topography. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a relatively level surface.
Unfortunately, a CMP process may not form a substantially planar surface across an entire semiconductor topography. In particular, the polishing rate of CMP may vary across a topography such that a semiconductor topography polished by a CMP process may have substantial elevational disparities. Such disparities may be particularly prevalent at an edge of the topography. For instance, a thickness of a semiconductor topography subsequent to chemical mechanical polishing may be greater at the edge of the topography than at an inner portion of the topography. The greater thickness of the semiconductor topography at its edge may be due to a slow polish rate at the edge of the topography as compared to polish rates at other regions of the topography. Several factors may influence the polish rates of a CMP process. For example, the polish rates may depend on the surface materials being polished or the rotational and lateral movement of the polishing pad relative to the semiconductor topography. Additional factors, which may affect polish rates of the CMP process, may include elements such as the polishing tool, the pad materials, the slurry, and interactions between these elements.
Some CMP tool manufacturers currently specify that their equipment is capable of forming a substantially planar surface across an area of a topography including the center of the topography and extending to a boundary 6 mm from the outer edge of the topography. However, such capabilities are difficult to obtain in practice with conventional CMP tools since the polishing process is so greatly dependent upon the condition of the incoming material. Practical and consistent capabilities of conventional CMP tools tend to result in a substantially planar surface in a region including the center of the topography and extending to a boundary at about 8 mm from the outer edge of the topography.
Elevational disparities which may be present on a semiconductor topography subsequent to chemical mechanical polishing may inhibit the formation of functional semiconductor devices on a portion of the semiconductor topography. For example, since the thickness of the semiconductor topography may be greater at an outer edge of the semiconductor topography than at an inner portion of the semiconductor topography, the thickness of the semiconductor topography at the outer edge may be outside the design specifications for a semiconductor device. Consequently, semiconductor devices formed at the outer edge of such a semiconductor topography may have dimensions which deviate significantly from design specifications. In this manner, acceptable devices may not be formed on an area of the semiconductor topography having such elevational disparities, thereby reducing the number of devices which may be formed on the semiconductor topography. As such, the presence of such elevational disparities on a semiconductor topography may reduce manufacturing yield and may increase production costs per semiconductor device.
Accordingly, it would be advantageous to develop a method and a system for increasing the amount of area across a semiconductor topography which is suitable for fabricating devices, including in a region near its outer edge.
The problems outlined above may be in large part addressed by a method and a system adapted for polishing a semiconductor topography. In particular, a method is provided which includes positioning a semiconductor topography against a carrier plate with a raised section. Such a method preferably allows a larger area capable of producing a target yield of semiconductor devices within dimensional specifications to be obtained than is obtained by positioning the topography against a carrier plate with a flat surface. The area producing such a target yield may be referred to as the area of the topography from which semiconductor devices may be suitably fabricated. More specifically, such an area preferably includes a substantially planar surface over which dimensional design specifications of subsequently formed devices may be met. As such, positioning a topography against a carrier plate with a raised section may form a substantially planar upper surface in a larger area than an area formed by positioning such a topography against a flat surface carrier plate. Furthermore, such a method is preferably conducted in a single polishing step. As such, a polishing system is provided which includes a carrier plate with a raised section adapted to planarize a semiconductor topography in a single polishing step.
In an embodiment, a polishing system may include a carrier plate with a raised section. Such a system may be adapted to planarize a semiconductor topography in a single polishing step. The use of the carrier plate with the raised section preferably allows a substantially planar surface to form across the topography in one polishing step. In some embodiments, the carrier plate may include multiple raised sections with which to form substantially planar surface in the single polishing step. The substantially planar surface may extend across a portion of the topography including the center of the topography to a boundary less than approximately 4 mm from the outer edge of the topography. In some embodiments, the boundary may be approximately 2 mm or less from the outer edge of the topography.
In addition, the dimensions of the raised section may be optimized such that a substantially planar upper surface of the semiconductor topography may be obtained in a single polishing step. For example, the raised section may be between approximately 0.0002 inches and approximately 0.005 inches thick. Moreover, the thickness variation of the raised section may be less than or equal to approximately 0.0005 inches. Alternatively, the thickness variation of the raised section may be more than approximately 0.0005 inches. In such an embodiment, the thickness of the raised section may vary continuously. In an alternative embodiment, the thickness of the raised section may vary such that steps of different thicknesses are formed. Furthermore, the cross-sectional lateral dimension of the raised section may be between approximately 1 mm and approximately 10 mm. More specifically, the cross-sectional lateral dimension of the raised section may be between approximately 2 mm and approximately 4 mm.
In conjunction with the aforementioned system, the method as described herein may include positioning the topography against a carrier plate with a raised section such that a larger area capable of producing a target yield of semiconductor devices within dimensional specifications may be obtained than is obtained by positioning the topography against a carrier plate with a flat surface. Such a target yield may be, for example, greater than 85%. In some embodiments, the target yield may be greater than 95%. In a preferred embodiment, the polishing process may include forming a substantially planar surface across the larger area in a single polishing step. The larger area may, for example, be a region of the semiconductor topography including the center of the topography and extending to a boundary less than approximately 4 mm from the outer edge of the topography. In some cases, the boundary may be approximately 2 mm or less from the outer edge of the topography.
In some embodiments, the polishing rate of the topography at the boundary of the subsequently formed larger area may be greater than or equal to the polishing rate of the center of the topography. More specifically, the polishing rate of the topography at the boundary of the subsequently formed larger area may be greater than the polishing rate of the center of the topography. In addition or alternatively, the polishing rate differential across the portion of the topography polished to form the larger area may less than approximately 10%. In another embodiment, the polishing rate differential across the portion of the topography polished to form the larger area may be less than approximately 5%. As such, the method as described herein may form a substantially planar surface across the larger area. For example, in an embodiment in which the polished topography includes a plurality of structures, the thickness of a structure arranged at the boundary of the larger area may differ by less than approximately 10% from a thickness of a corresponding structure arranged within the center of the topography.
As stated above, the method may include planarizing the topography in a single step. In such an embodiment, the planarizing step may include positioning the topography against a carrier plate which includes a raised section. In particular, the planarizing process may include positioning the topography against the surface of the carrier plate that includes the raised section. In an embodiment, the raised section may include a lip arranged at the edge of the carrier plate. The planarizing process may further include forming a substantially planar surface in a region of the topography including the center of the topography to a boundary less than approximately 4 mm from the outer edge of the topography. In some embodiments, such a region may extend to a boundary approximately 2 mm or less from the outer edge of the topography. In a preferred embodiment, the amount of the semiconductor topography removed during the planarizing process may vary by less than approximately 10% across the portion of the topography planarized to form the aforementioned region. In some embodiments, the amount of the semiconductor topography removed during the planarizing process may vary by less than approximately 5% across the portion of the topography planarized to form such a region.
There may be several advantages to forming a substantially planar upper surface upon a semiconductor topography. For example, a functional semiconductor device may be formed in a region extending less than approximately 8 mm from the outer edge of a semiconductor substrate. In some cases, the method as described herein may allow semiconductor devices to be formed in a region of the topography extending less than approximately 6 mm from the outer edge of the topography. The formation of functional semiconductor devices within such a relatively close vicinity of the outer edge of the substrate may allow for an increase in the number of devices that may be formed upon a substrate. Such an increase in semiconductor device formation upon a substrate may increase manufacturing yield and may reduce production costs per semiconductor device.